The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2010

Filed:

Sep. 29, 2006
Applicants:

Chad Kendall, Burnaby, CA;

Scott Mcdaniel, Villa Park, CA (US);

Sunil Pulikkal, Tustin, CA (US);

Inventors:

Chad Kendall, Burnaby, CA;

Scott McDaniel, Villa Park, CA (US);

Sunil Pulikkal, Tustin, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus for providing a bus interface are disclosed. An example method for providing a bus interface includes operating first circuitry using a first power supply voltage in a normal operating mode, where the first circuitry includes at least a portion of datapath circuitry of the bus interface. The example method further includes powering down the first circuitry in a low power operating mode and operating second circuitry using the first power supply voltage in the normal operating mode. The example method also includes operating the second circuitry using a second power supply voltage in the low power operating mode. The second circuitry includes a power management control circuit adapted to receive a power management event indication signal. Responsive to the power management event indication signal, the control circuit provides at least one of an in-band power management indication and an out-of-band power management indication to one or more devices in a computing system. In the example method, the first and second power supply voltages may be provided by a single power supply or, alternatively, by multiple power supplies.


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