The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2010

Filed:

Nov. 01, 2004
Applicants:

Terry C. Brown, Austin, TX (US);

Christopher R. Hansen, Grass Valley, CA (US);

Jeffrey C. Strait, Reno, NV (US);

Ravi G. Mantri, Hillsboro, OR (US);

Felician Bors, Grass Valley, CA (US);

Inventors:

Terry C. Brown, Austin, TX (US);

Christopher R. Hansen, Grass Valley, CA (US);

Jeffrey C. Strait, Reno, NV (US);

Ravi G. Mantri, Hillsboro, OR (US);

Felician Bors, Grass Valley, CA (US);

Assignee:

Metanoia Technologies, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 27/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A multicarrier transceiver is disclosed that includes a digital signal processor with a plurality of memory locations, a direct memory, an encoder module coupled to receive data from the FIFO buffers, a decoder module coupled to receive data from the FIFO buffers, a Fourier transform module configured to perform an inverse Fast Fourier transform for transmit operations and to perform Fast Fourier transform (FFT) operations for receive operations, a plurality of distributed modules including the encoder module, the decoder module and the Fourier transform module, each module configured with a memory port, each memory port coupled to a peripheral bus and the DMA bus, a plurality of memory ports coupled to each of the distributed modules, the plurality of memory ports coupled to a peripheral bus, and a plurality of point-to-point buses coupled to each of the distributed modules, the point-to-point bus configured to enable data flow and testing and provide a bypass capability for each of the distributed modules.


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