The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2010
Filed:
Aug. 23, 2006
Bruce C. Schmukler, Duluth, GA (US);
Arvind Raghavan, Waltham, MA (US);
Ziba Nami, Duluth, GA (US);
Jyothi Emmanuel Peddi, Austell, GA (US);
Andrew Joo Kim, Atlanta, GA (US);
Michael G. Vrazel, Chamblee, GA (US);
Charles E. Summers, Woodstock, GA (US);
Bruce C. Schmukler, Duluth, GA (US);
Arvind Raghavan, Waltham, MA (US);
Ziba Nami, Duluth, GA (US);
Jyothi Emmanuel Peddi, Austell, GA (US);
Andrew Joo Kim, Atlanta, GA (US);
Michael G. Vrazel, Chamblee, GA (US);
Charles E. Summers, Woodstock, GA (US);
Quellan, Inc., Atlanta, GA (US);
Abstract
A circuit can process a sample of a signal to emulate, simulate, or model an effect on the signal. Thus, an emulation circuit can produce a representation of a real-world signal transformation by processing the signal according to one or more signal processing parameters that are characteristic of the real-world signal transformation. The emulation circuit can apply analog signal processing and/or mixed signal processing to the signal. The signal processing can comprise feeding the signal through two signal paths, each having a different delay, and creating a weighted sum of the outputs of the two signal paths. The signal processing can also (or alternatively) comprise routing the signal through a network of delay elements, wherein a bank of switching or routing elements determines the route and thus the resulting delay.