Programmable logic block having reduced output delay during ram write processes when programmed to function in ram mode

Abstract

A programmable logic block provides an improved output delay by bypassing the memory array and multiplexer structure when programmed to function as a random access memory (RAM) and a new value is written to the RAM. A programmable logic block includes memory cells, a multiplexer structure, a memory element, a bypass select multiplexer, and a control circuit. The memory cells implement a RAM driven by a write data input signal and a write enable signal. Each memory cell drives an input terminal of the multiplexer structure. Under the control of the write enable signal, a bypass select multiplexer selects either the write data input signal (in RAM mode) or the output terminal of the multiplexer structure (in another mode), and passes the selected signal to a memory element. Thus, when in RAM mode, write data is simultaneously written to a specified location in the RAM and to the memory element.