The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2010
Filed:
Jan. 07, 2005
Koen Reynders, Oudenaarde, BE;
Peter Moens, Zottegem, BE;
Koen Reynders, Oudenaarde, BE;
Peter Moens, Zottegem, BE;
Semiconductor Components Industries, L.L.C., Phoenix, AZ (US);
Abstract
A circuit for protecting a semiconductor from electrostatic discharge events includes a Zener diode () in series with a resistor () between a power line HV VDD and a ground fine HV VSS. A gate of a DMOS device () is connected to a node between the diode and the resistor. The drain and source of the DMOS are connected between the power lines. During an ESD event, the gate voltage of the DMOS increases and the ESD current will be discharged through the DMOS to ground. When the current exceeds the capacity of the channel of the DMOS, a parasitic bipolar transistor or transistors associated with the DMOS device acts in a controlled snapback to discharge the current to ground. The use of a vertical DMOS (VDMOS) instead of a lateral DMOS (LDMOS), can reduce the area of the device and improve the protection.