The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2010
Filed:
Oct. 31, 2007
Hee-soo Kang, Anyang-si, KR;
Dong-gun Park, Seongnam-si, KR;
Choong-ho Lee, Seongnam-si, KR;
Hye-jin Cho, Seongnam-si, KR;
Young-joon Ahn, Daejeon Metropolitan, KR;
Hee-soo Kang, Anyang-si, KR;
Dong-gun Park, Seongnam-si, KR;
Choong-ho Lee, Seongnam-si, KR;
Hye-Jin Cho, Seongnam-si, KR;
Young-Joon Ahn, Daejeon Metropolitan, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first opening in the mask layer to expose a first gate region in the cell area of the semiconductor substrate, and then forming a FinFET gate electrode in the first opening using a damascene process. A MOSFET gate fabricated by forming a second opening in the mask layer to expose a second gate region in the peripheral circuit area of the semiconductor substrate, and then forming a MOSFET gate electrode in the second opening using a damascene process.