The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2010
Filed:
Feb. 06, 2006
Ann Witvrouw, Herent, BE;
Chris Van Hoof, Leuven, BE;
Raquel Consuelo Hellin Rico, Elda (Alicante), ES;
Anthony Joseph Muscat, Tucson, AZ (US);
Jan Fransaer, Leefdaal, BE;
Jean-pierre Celis, Korbeek-Lo, BE;
Ann Witvrouw, Herent, BE;
Chris Van Hoof, Leuven, BE;
Raquel Consuelo Hellin Rico, Elda (Alicante), ES;
Anthony Joseph Muscat, Tucson, AZ (US);
Jan Fransaer, Leefdaal, BE;
Jean-Pierre Celis, Korbeek-Lo, BE;
IMEC, Leuven, BE;
Katholieke Universiteit Leuven, K.U. Leuven R&D, Lueven, BE;
Abstract
Manufacturing a semiconductor device involves forming () a sacrificial layer where a micro cavity is to be located, forming () a metal layer of thickness greater than 1 micron over the sacrificial layer, forming () a porous layer from the metal layer, the porous layer having pores of length greater than ten times their breadth, and having a breadth in the range 10 nm-500 nanometers. The pores can be created by anodising, electrodeposition or dealloying. Then the sacrificial layer can be removed () through the porous layer, to form the micro cavity, and pores can be sealed (). Encapsulating MEMS devices with a porous layer can reduce costs by avoiding using photolithography for shaping the access holes since the sacrificial layer is removed through the porous membrane.