The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2010

Filed:

Jan. 09, 2007
Applicants:

William J. Armstrong, Rochester, MN (US);

Richard L. Arndt, Austin, TX (US);

Michael J. Corrigan, Rochester, MN (US);

Giles R. Frazier, Austin, TX (US);

Timothy R. Marchini, Hyde Park, NY (US);

Cathy May, Millwood, NY (US);

Naresh Nayar, Rochester, MN (US);

John T. O'quin, Ii, Austin, TX (US);

Inventors:

William J. Armstrong, Rochester, MN (US);

Richard L. Arndt, Austin, TX (US);

Michael J. Corrigan, Rochester, MN (US);

Giles R. Frazier, Austin, TX (US);

Timothy R. Marchini, Hyde Park, NY (US);

Cathy May, Millwood, NY (US);

Naresh Nayar, Rochester, MN (US);

John T. O'Quin, II, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a 'processor compatibility register' (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.


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