The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2010
Filed:
Mar. 04, 2008
Siew Sin Hiew, San Jose, CA (US);
Charles C. Lee, Cupertino, CA (US);
I-kang Yu, Palo Alto, CA (US);
Abraham Chih-kang MA, Fremont, CA (US);
Ming-shiang Shen, Taipei Hsien, TW;
Siew Sin Hiew, San Jose, CA (US);
Charles C. Lee, Cupertino, CA (US);
I-Kang Yu, Palo Alto, CA (US);
Abraham Chih-Kang Ma, Fremont, CA (US);
Ming-Shiang Shen, Taipei Hsien, TW;
Super Talent Electronics, Inc., San Jose, CA (US);
Abstract
Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.