Method and apparatus for generating high-frequency command and address signals for high-speed semiconductor memory device testing

Abstract

A method and system for testing a semiconductor memory device using low-speed test equipment. The method includes providing a high-frequency test pattern by grouping a command signal and an address signal into command signal groups and address signal groups each corresponding to L cycles of a clock signal output from automatic test equipment (ATE) where L is a natural number. A valid command signal and a valid address signal, which are not in an idle state, are extracted from each of a plurality of command signal groups and each of a plurality of address signal groups. The valid command signal and the valid address signal are compressed into signals having a length corresponding to 1/M (M is a natural number larger than 1) of the cycle of the clock signal where M is a natural number larger than 1. A position designating signal indicating the positions of the valid command signal and the valid address signal in each command signal group and each address signal group is generated. A high-frequency command signal and a high-frequency address signal from the compressed valid command signal and the compressed valid address signal using the position designating signal are generated.