The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2010

Filed:

Jul. 23, 2007
Applicants:

Yu Qing Cheng, Santa Clara, CA (US);

John Gregory Favor, Santa Clara, CA (US);

Carlos Puchol, Sunnyvale, CA (US);

Seungyoon Peter Song, San Jose, CA (US);

Peter Glaskowsky, Cupertino, CA (US);

Laurent Moll, San Jose, CA (US);

Joe Rowlands, Santa Clara, CA (US);

Donald Alpert, Phoenix, AZ (US);

Inventors:

Yu Qing Cheng, Santa Clara, CA (US);

John Gregory Favor, Santa Clara, CA (US);

Carlos Puchol, Sunnyvale, CA (US);

Seungyoon Peter Song, San Jose, CA (US);

Peter Glaskowsky, Cupertino, CA (US);

Laurent Moll, San Jose, CA (US);

Joe Rowlands, Santa Clara, CA (US);

Donald Alpert, Phoenix, AZ (US);

Assignee:

Oracle America, Inc., Redwood City, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present disclosure provides methods and systems adapted for use with a processor having one or more physical cores. The methods and systems include a virtual core management component adapted to map one or more virtual cores to at least one of the physical cores to enable execution of one or more programs by the at least one physical core. The one or more virtual cores include one or more logical states associated with the execution of the one or more programs. The methods and systems may include a memory component adapted to store the one or more virtual cores. The virtual core management component may be adapted to transfer the one or more virtual cores from the memory component to the at least one physical core.


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