The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2010

Filed:

Apr. 11, 2007
Applicant:

Igor Blednov, Nijmegen, NL;

Inventor:

Igor Blednov, Nijmegen, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/68 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated Doherty amplifier structure comprises an input bond pad (IBP), and an output bond pad (OBP). A first transistor (T) forms the peak amplifier stage of the Doherty amplifier and has a control input (G) to receive a first input signal (IS) being an input signal of the Doherty amplifier, and has an output (D) to supply an amplified first input signal (OS) at an output of the Doherty amplifier A second transistor (T) forms a main amplifier stage of the Doherty amplifier and has a control input (G) to receive a second input signal (IS) and has an output (D) to supply an amplified second input signal (S). The first input signal (IS) and the second input signal (IS) have a 90° phase offset. A first bond wire (BW) forms a first inductance (L), and extends in a first direction, and is arranged between the input bond pad (IBP) and the control input (G) of the first transistor (T). A second bond wire (B W) forms a second inductance (L), and extends in the first direction, and is arranged between the output bond pad (OBP) and the output (D) of the first transistor (T). A third bond wire (B W) forms a third inductance (L) and extends in a second direction substantially perpendicular to the first direction, and is arranged between the output (D) of the first transistor (T) and the output (D) of the second transistor (T).


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