The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2010

Filed:

Jun. 15, 2009
Applicants:

Andy L. Lee, San Jose, CA (US);

Wanli Chang, Saratoga, CA (US);

Cameron Mcclintock, Mountainview, CA (US);

John E. Turner, Santa Cruz, CA (US);

Brian D. Johnson, Sunnyvale, CA (US);

Chiao Kai Hwang, Fremont, CA (US);

Richard Yen-hsiang Chang, East Palo Alto, CA (US);

Richard G. Cliff, Los Altos, CA (US);

Inventors:

Andy L. Lee, San Jose, CA (US);

Wanli Chang, Saratoga, CA (US);

Cameron McClintock, Mountainview, CA (US);

John E. Turner, Santa Cruz, CA (US);

Brian D. Johnson, Sunnyvale, CA (US);

Chiao Kai Hwang, Fremont, CA (US);

Richard Yen-Hsiang Chang, East Palo Alto, CA (US);

Richard G. Cliff, Los Altos, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
Abstract

Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Von the range of signals passed by single-transistor passgates is reduced. In one arrangement, the V-Vlimit for signals propagated through NMOS passgates is raised by applying a higher V; in another arrangement, the Vis lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.


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