The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2010

Filed:

Dec. 05, 2008
Applicants:

Hare K Verma, Bangalore, IN;

Manoj Gunwani, Vallejo, CA (US);

Conrad Kong, San Jose, CA (US);

Jai Liu, San Ramon, CA (US);

Nilanjan Chatterjee, Cupertino, CA (US);

Inventors:

Hare K Verma, Bangalore, IN;

Manoj Gunwani, Vallejo, CA (US);

Conrad Kong, San Jose, CA (US);

Jai Liu, San Ramon, CA (US);

Nilanjan Chatterjee, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic blocks, and programmable logic interfaces. The programmable logic interfaces couple the programmable logic blocks to external interfaces of the field programmable ASIC, and enable the programmable logic array to be inserted into the field programmable ASIC as a hard macro block.


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