The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Oct. 22, 2007
George J. Chen, Union City, CA (US);
Darryl J. Gove, Sunnyvale, CA (US);
Robert E. Mains, Morgan Hill, CA (US);
George J. Chen, Union City, CA (US);
Darryl J. Gove, Sunnyvale, CA (US);
Robert E. Mains, Morgan Hill, CA (US);
Oracle America, Inc., Redwood City, CA (US);
Abstract
A method and apparatus for executing multithreaded algorithm to provide static timing analysis of a chip design includes analyzing a chip design to identify various components and nodes associated with the components. A node tree is built with a plurality of nodes. The node tree identifies groups of nodes that are available in different levels. A size of node grouping for a current level is determined by looking up the node tree. Testing data for parallel processing of different size of node groupings using varied thread counts is compiled. An optimum thread count for the current level based on the size of node grouping in the node tree is identified from compiled testing data. Dynamic parallel processing of nodes in the current level is performed using the number of threads identified by the optimum thread count. An acceptable design of the chip is determined by the dynamic parallel processing.