The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Sep. 11, 2007
Sandip Bag, Karnataka, IN;
Manoj Dusanapudi, Karnataka, IN;
Sunil Suresh Hatti, Karnataka, IN;
Shakti Kapoor, Austin, TX (US);
Batchu Naga Venkata Satyanarayana, Karnataka, IN;
Sandip Bag, Karnataka, IN;
Manoj Dusanapudi, Karnataka, IN;
Sunil Suresh Hatti, Karnataka, IN;
Shakti Kapoor, Austin, TX (US);
Batchu Naga Venkata Satyanarayana, Karnataka, IN;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method for re-executing a test case and modifying the test case's effective addresses, effective segment identifiers (ESIDs), and virtual segment identifiers (VSIDs) in order to fully test a processor's SLB and TLB cells is presented. A test case generator generates a test case that includes an initial set of test case effective addresses, an initial set of ESIDs, and an initial set of VSIDs. The test case executor uses an effective address arithmetic function and a virtual address arithmetic function to modify the test case effective addresses, the ESIDs, and the VSIDs on each re-execution that, in turn, sets/unsets each bit within each SLB and TLB entry. In one embodiment, the invention described herein sequentially shifts segment lookaside buffer entries, whose ESIDs are in single bit increments, in order to fully test each ESID bit location within each SLB entry.