Enhancing performance of a memory unit of a data processing device by separating reading and fetching functionalities

Abstract

The present invention relates to a data processing device () comprising a processing unit () and a memory unit (), and to a method for controlling operation of a memory unit () of a data processing device. The memory unit () comprises a main memory (), a low- level cache memory (), which is directly connected to the processing unit () and adapted to hold all pixels of a currently active sliding search area for reading access by the processing unit (), a high-level cache memory (), which is connected between the low-level cache memory and the frame memory, and a first pre-fetch buffer (), which is connected between the high-level cache memory and the low- level cache memory and which is adapted to hold one search-area column or one search-area line of pixel blocks, depending on the scan direction and scan order followed by the processing unit. Reading and fetching functionalities are decoupled in the memory unit (). The fetching functionality is concentrated on the higher cache level, while the reading functionality is concentrated on the lower cache level. This way concurrent reading and fetching can be achieved, thus enhancing the performance of a data processing device.