The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
May. 30, 2007
Chaoliang T. Chen, Irvine, CA (US);
Tracy Denk, Aliso Viejo, CA (US);
Nabil R. Yousef, Foothill Ranch, CA (US);
Philip Treigherman, Newport Beach, CA (US);
Chaoliang T. Chen, Irvine, CA (US);
Tracy Denk, Aliso Viejo, CA (US);
Nabil R. Yousef, Foothill Ranch, CA (US);
Philip Treigherman, Newport Beach, CA (US);
Newport Media, LLC, Lake Forest, CA (US);
Abstract
Location cache memory architectures that only require 32 Kbits or less per frame to store erasure information with simple address mapping to the main MPE-FEC RAM for easy column-wise and row-wise access. Alternative architectures are designed to greatly reduce the size and logic complexity of the MPE-FEC erasure cache memory. Two architectures reduce the erasure cache size down to 32 Kbits and 28 Kbits, correspondingly, without introducing additional erasure locations, while another architecture further reduces the required memory size down to 16K, 8K, 4K, or 2K bits with a slight increase in the total erasure locations. All architectures group the data in MPE-FEC frame memory into blocks of 2consecutive bytes and use one or a few bits to store the erasure status in each block, thereby, greatly reducing the required cache memory size.