The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2010

Filed:

Feb. 07, 2008
Applicants:

Alaa El-agha, Waterloo, CA;

Dustin Griesdorf, Waterloo, CA;

Gareth P. Weale, New Hamburg, CA;

Jakob Nielson, Waterloo, CA;

Inventors:

Alaa El-Agha, Waterloo, CA;

Dustin Griesdorf, Waterloo, CA;

Gareth P. Weale, New Hamburg, CA;

Jakob Nielson, Waterloo, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03C 3/00 (2006.01); H03K 7/06 (2006.01); H04L 27/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method, system and digital modulator for modulation are provided The modulator includes a dividing mechanism for dividing a reference clock by a divide value to produce a modulated signal associated with at least one input data, and a control unit for providing at least one divide sequence to the dividing mechanism. The at least one divide sequence includes a sequence of one or more divide values. The divide value of the divide sequence is configurable and selectively provided to the dividing mechanism based on the at least one input data. The method includes configuring at least one divide sequence including a sequence of one or more divide values, and selecting a divide value from the at least one divide sequence based on at least one input data. The method includes dividing a reference clock by the selected divide value and generating a modulated signal based on the divide operation. The system for modulation-based commutations link includes a modulation unit having a dividing mechanism for dividing a reference clock by a divide value, and a configuration register for one or more configurable divide sequences.


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