Pll-based timing-signal generator and method of generating timing signal by same

Abstract

A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency F, the PLL outputs M voltage controlled signals with the same frequency F=N*Fand equally distributed phase differences. The rising/falling edge generating unit is for generating a rising point signal and a falling point signal corresponding to respective ones one of M*P candidate timing points which are defined in a cycle of the reference signal according to the M voltage controlled signals. The timing-signal generating unit coupled to the rising/falling edge generating unit is for generating a timing signal which toggles high in response to the rising point signal and toggles low in response to the falling point signal.