The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
May. 19, 2009
Bobby Yang, Los Altos Hills, CA (US);
Reto Stamm, Sunnyvale, CA (US);
Stephen M. Trimberger, San Jose, CA (US);
Christopher H. Kingsley, Longmont, CO (US);
Bobby Yang, Los Altos Hills, CA (US);
Reto Stamm, Sunnyvale, CA (US);
Stephen M. Trimberger, San Jose, CA (US);
Christopher H. Kingsley, Longmont, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A defect is automatically isolated in an integrated circuit device having programmable logic and interconnect circuits. A sequence of configurations is created to route data in a pattern through the programmable logic and interconnect circuits. Each configuration within the sequence is determined (e.g., generated or selected from a plurality of pre-generated configurations) as a function of output data from a prior configuration in the sequence. For each configuration in the sequence, the programmable logic and interconnect circuits are configured with the configuration and an automatic test instrument routes data in the pattern through the programmable logic and interconnect circuits. For each configuration in the sequence, the output data from the programmable logic and interconnect circuits is assessed. For each configuration in the sequence, the assessed output data isolates the defect to a portion of the pattern for the configuration that is within the portion for a prior configuration in the sequence.