The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Dec. 30, 2008
Young Jin Lee, Yongin-si, KR;
Dong Sun Sheen, Yongin-si, KR;
Seok Pyo Song, Seongnam-si, KR;
MI RI Lee, Icheon-si, KR;
Chi Ho Kim, Jeonju-si, KR;
Gil Jae Park, Busan-si, KR;
BO Min Seo, Yongin-si, KR;
Young Jin Lee, Yongin-si, KR;
Dong Sun Sheen, Yongin-si, KR;
Seok Pyo Song, Seongnam-si, KR;
Mi Ri Lee, Icheon-si, KR;
Chi Ho Kim, Jeonju-si, KR;
Gil Jae Park, Busan-si, KR;
Bo Min Seo, Yongin-si, KR;
Hynix Semiconductor Inc., Icheon-si, KR;
Abstract
A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a first metal layer that is in contact with the first silicon pattern and the exposed first portion of the silicon substrate; and forming a first gate, a first junction, a second gate, and a second junction by performing a heat treatment to silicify the respective first and second silicon patterns and the silicon substrate.