The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2010
Filed:
Jan. 12, 2006
Kenneth J. Goodnow, Essex, VT (US);
Clarence R. Ogilvie, Huntington, VT (US);
Christopher B. Reynolds, Underhill, VT (US);
Sebastian T. Ventrone, South Burlington, VT (US);
Paul S. Zuchowski, Jericho, VT (US);
Kenneth J. Goodnow, Essex, VT (US);
Clarence R. Ogilvie, Huntington, VT (US);
Christopher B. Reynolds, Underhill, VT (US);
Sebastian T. Ventrone, South Burlington, VT (US);
Paul S. Zuchowski, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.