The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2010

Filed:

Dec. 04, 2006
Applicants:

Murat R. Becer, Cedar Park, TX (US);

Joao M. Geada, Chelmsford, MA (US);

Lee LA France, Bolton, MA (US);

Nicholas Rethman, North Andover, MA (US);

Qian Shen, Shrewsbury, MA (US);

Inventors:

Murat R. Becer, Cedar Park, TX (US);

Joao M. Geada, Chelmsford, MA (US);

Lee La France, Bolton, MA (US);

Nicholas Rethman, North Andover, MA (US);

Qian Shen, Shrewsbury, MA (US);

Assignee:

CLK Design Automation, Inc., Littleton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 17/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system for circuit timing analysis includes a database for holding results of execution of portions of a timing analysis computation. Multiple computation modules are configured for concurrent execution of the portions of a timing analysis computation, for example, a static circuit timing analysis computation. A control subsystem is coupled to the database and to the computation modules, and is configured to receive results of the portions of the computation from the computation modules and to update the database using the received results. Based on the received results, the control module selects further portions of the computations for computation and assign each selected portion to one of the computation modules. The system makes use of parallel processing that is arranged in a way that avoids bottlenecks, such as at least some memory access bottlenecks resulting from data structure locking.


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