The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2010

Filed:

Apr. 25, 2005
Applicants:

Kazuaki Tamura, Osaka, JP;

Tomoaki Izumi, Osaka, JP;

Tetsushi Kasahara, Osaka, JP;

Masahiro Nakanishi, Kyoto, JP;

Kiminori Matsuno, Osaka, JP;

Manabu Inoue, Osaka, JP;

Inventors:

Kazuaki Tamura, Osaka, JP;

Tomoaki Izumi, Osaka, JP;

Tetsushi Kasahara, Osaka, JP;

Masahiro Nakanishi, Kyoto, JP;

Kiminori Matsuno, Osaka, JP;

Manabu Inoue, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/03 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device in which data is not written in a transfer destination under a state including an error when an error occurs at the time of reading data at the transfer destination. The semiconductor memory device () comprising a nonvolatile memory () having a data writing unit smaller than a physical block is provided with an error detecting/correcting circuit () in the non-volatile memory (). When data stored in a specified block of the non-volatile memory () is transferred to a different physical block and written, the error detecting/correcting circuit () performs error detection and correction of data.


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