Memory control circuit and microprocessory system for pre-fetching instructions

Abstract

A memory control circuit for providing a small-circuit-size memory control circuit capable of reducing a branch penalty during the execution of a branch instruction in a CPU. A branch-destination buffer caches a branch-destination instruction and a branch-destination-instruction address determined by a branch instruction executed by the CPU. When the CPU executes a branch instruction thereafter, if the branch-destination-instruction address output from the CPU matches an instruction address in the branch-destination buffer, the corresponding branch-destination instruction stored in the branch-destination buffer is sent to the CPU. When a branch instruction is executed, an address comparison circuit compares the branch-destination-instruction address with the branch-source-instruction address. A buffer-update control circuit updates data of the branch-destination buffer by the branch-destination instruction only when it is determined according to the result of comparison performed by the address comparison circuit that the instruction address has been changed in the negative direction by the instruction branch.