Efficient handling of vector high-level language conditional constructs in a simd processor

Abstract

The present invention provides an efficient method to implement nested if-then-else conditional statements in a SIMD processor, which requires only one vector compare instruction for both if and else parts of the conditional construct. No stack and stack-handling instructions are needed for vector condition codes. Two condition code flag bits representing if and else parts of testing per element provide for nesting of multiple if-then-else. All SIMD instructions are conditional including the vector compare instruction, and this provides a method for aggregating multiple conditions in nested if-then-else statements. M full levels of if-then-else nesting requires (2−1) nodes or vector test instructions and 2condition code flags per vector element. Also, capability to compare any element of first source vector register with any element of second source vector is provided.