The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2010
Filed:
Sep. 08, 2006
Laura Sartori, I-45030 Occhiobello (RO), IT;
Adamo Corsi, I-20099 Sesto San Giovanni (MI), IT;
Marco Roveda, I-20086 Motta Visconti (PC), IT;
Giuseppe Maurizio Lorusso, I-70026 Modugno (BA), IT;
Daniela Ruggeri, I-98168 Messina, IT;
Demetrio Pellicone, I-20052 Monza (MI), IT;
Laura Sartori, I-45030 Occhiobello (RO), IT;
Adamo Corsi, I-20099 Sesto San Giovanni (MI), IT;
Marco Roveda, I-20086 Motta Visconti (PC), IT;
Giuseppe Maurizio Lorusso, I-70026 Modugno (BA), IT;
Daniela Ruggeri, I-98168 Messina, IT;
Demetrio Pellicone, I-20052 Monza (MI), IT;
Other;
Abstract
A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.