Long latency interface protocol

Abstract

An interface supports a signaling protocol between a first hardware component and a second hardware component. The interface includes a first pin to provide a first clock signal sourced from the first hardware component to the second hardware component during a first operation, the first operation being an operation in which data is being transferred from the first hardware component to the second hardware component. A second pin to receive a second clock signal sourced from the second hardware component during a second operation, the second operation being an operation in which data is being transferred from the second hardware component to the first hardware component. A third pin to provide a first gate control signal sourced from the first hardware component to the second hardware component, the first gate control signal to synchronize data transfer between the first hardware component and the second hardware component during both the first operation and the second operation. The first gate control signal is gated based on the first clock signal or the second clock signal.