The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2010
Filed:
May. 15, 2007
Applicants:
Bin Wang, Seattle, WA (US);
Shih-hsin Wang, San Jose, CA (US);
William T. Colleran, Seattle, WA (US);
Inventors:
Bin Wang, Seattle, WA (US);
Shih-Hsin Wang, San Jose, CA (US);
William T. Colleran, Seattle, WA (US);
Assignee:
Virage Logic Corporation, Fremont, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract
NVM arrays include rows and columns of NVM cells comprising a floating gate and a four transistor storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.