On silicon interconnect capacitance extraction

Abstract

The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit () comprises signal generation means () for generating a periodical pulse signal connected to first and to second signal delaying means () for respective delaying said pulse signal, wherein said second signal delaying means () are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate () for connecting respective first and said second delay signals of said respective first and second delay means (), said logical XOR gate () being connected to signal integrating means (); and said signal integrating means () being connected to analog to digital converting means (). Whilst the error in conventional uncompensated systems, like delay line only, the error can be up to 30%, in the circuit according to the invention, the error due to process variations in the front-end is about 2%. Further, an output is provided in a digital format and thus, can be measured quickly with simple external hardware. Furthermore, the pulse signal frequency can be used as a monitor to measure process variations in the front-end. Moreover, since the circuit () is remarkably accurate and very easy to measure, it is the best choice as a process monitor for every chip fabricated in the future.