The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2010
Filed:
Sep. 17, 2009
Samuel S. S. Choi, Hopewell Juction, NY (US);
Lawrence A. Clevenger, Hopewell Junction, NY (US);
Maxime Darnon, Yorktown Heights, NY (US);
Daniel C. Edelstein, Yorktown Heights, NY (US);
Satyanarayana Venkata Nitta, Yorktown Heights, NY (US);
Shom Ponoth, Albany, NY (US);
Pak Leung, Cedar Park, TX (US);
Samuel S. S. Choi, Hopewell Juction, NY (US);
Lawrence A. Clevenger, Hopewell Junction, NY (US);
Maxime Darnon, Yorktown Heights, NY (US);
Daniel C. Edelstein, Yorktown Heights, NY (US);
Satyanarayana Venkata Nitta, Yorktown Heights, NY (US);
Shom Ponoth, Albany, NY (US);
Pak Leung, Cedar Park, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Freescale Semiconductor Inc., Austin, TX (US);
Abstract
Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.