The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2010
Filed:
Mar. 08, 2005
Hideki Iwaki, Ibaraki, JP;
Tetsuyoshi Ogura, Settsu, JP;
Naoki Komatsu, Moriguchi, JP;
Takeshi Nakayama, Katano, JP;
Tomohiro Kinoshita, Katano, JP;
Hideki Iwaki, Ibaraki, JP;
Tetsuyoshi Ogura, Settsu, JP;
Naoki Komatsu, Moriguchi, JP;
Takeshi Nakayama, Katano, JP;
Tomohiro Kinoshita, Katano, JP;
Panasonic Corporation, Osaka, JP;
Abstract
An interference analysis device can be provided, which analyzes interference between wirings of a circuit board with reduced load and for a short time period. The interference analysis device according to the present invention includes: a design data input part for inputting design data of the circuit board; a noise characteristics setting part that sets data representing electrical characteristics of noise for a wiring of the circuit board; a limit value setting part that sets an allowable limit value of noise received by a wiring; a selection part that selects a wiring group to be analyzed based on the noise characteristics data and the allowable limit value; an interference analysis part that calculates, concerning the selected wiring group, an amount of interference from a wiring giving the interference to a wiring receiving the interference; and a received noise level calculation part that calculates a noise level that the wiring receiving the interference will receive.