The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2010
Filed:
Sep. 30, 2008
Gwen G. Liang, Palo Alto, CA (US);
William Bradley Vest, San Jose, CA (US);
Gwen G. Liang, Palo Alto, CA (US);
William Bradley Vest, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Circuits and methods for reducing power consumption in an Integrated Circuit (IC) are provided. In one embodiment, a circuit includes a POR system control circuit, a POR latch and a control block circuit. The POR system control circuit generates a pulse during power up which is sent to the POR latch to set the state of the POR latch to a first logic state. The state of the POR latch is used to enable POR circuits during power up. The control block generates an output to disable POR circuits in the IC based on the state of the POR latch. After power-up, the state of the POR latch is set to a second logic state in order to disable the POR circuits resulting in power savings in the IC by eliminating static POR circuit current.