The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2010

Filed:

May. 06, 2008
Applicants:

Craig S. Forrest, San Francisco, CA (US);

Robert J. Drost, Los Altos, CA (US);

Ronald Ho, Mountain View, CA (US);

Ivan E. Sutherland, Santa Monica, CA (US);

Inventors:

Craig S. Forrest, San Francisco, CA (US);

Robert J. Drost, Los Altos, CA (US);

Ronald Ho, Mountain View, CA (US);

Ivan E. Sutherland, Santa Monica, CA (US);

Assignee:

Oracle America, Inc., Redwood Shores, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01J 1/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together with their pads facing each other. The PxC links may be directly between the chips or through an intermediate passive bridge chip. The interface chip is coupled to an external optical channel and includes converters between optical and electrical signals, control circuitry, buffers, and PxC elements for communicating with the memory chips. The array of memories may be a linear or two-dimensional array around the interface chip forming a redundant PxC network, optionally with redundant PxC connections. Multiple rectangular memory chips may present their narrow sides to the interface chip to maximize bandwidth.


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