The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7785951 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 31, 2010

Filed:

Jul. 31, 2007
Applicants:

Seo-woo Nam, Gyeonggi-do, KR;

Il-young Yoon, Gyeonggi-do, KR;

Jae-ouk Choo, Gyeonggi-do, KR;

Hong-jae Shin, Seoul, KR;

Nae-in Lee, Seoul, KR;

Inventors:

Seo-woo Nam, Gyeonggi-do, KR;

Il-young Yoon, Gyeonggi-do, KR;

Jae-ouk Choo, Gyeonggi-do, KR;

Hong-jae Shin, Seoul, KR;

Nae-in Lee, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.


Find Patent Forward Citations

Nam, Seo-woo. (2010). Methods of forming integrated circuit devices having tensile and compressive stress layers therein and devices formed thereby (U.S. Patent No. 7785951). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7785951

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