The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2010

Filed:

Mar. 30, 2007
Applicants:

Kazuyo Nishikawa, Osaka, JP;

Masahiro Ueminami, Kyoto, JP;

Tadashi Nitta, Kyoto, JP;

Inventors:

Kazuyo Nishikawa, Osaka, JP;

Masahiro Ueminami, Kyoto, JP;

Tadashi Nitta, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device comprises an address terminal through which an address for reading out stored data in a memory array is input, a clock input terminal through which an input clock is input, a data output terminal through which data read out from the memory array in accordance with the address is output, and a clock output terminal through which an output clock synchronous with the input clock is output. The clock output terminal invariably outputs one of a first voltage and a second voltage. Only when valid data is output from the data output terminal, the clock output terminal causes an output voltage to go from the first voltage to the second voltage or from one voltage to the other voltage.


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