Successive approximation analog-to-digital converter with inbuilt redundancy

Abstract

The method and system for converting an analog value into a digital equivalent using a plurality of conversion engines are disclosed. In one embodiment the plurality of conversion engines comprise N DACs associated with M comparators, wherein M is substantially greater than N, wherein M and N are integers, wherein each of the N CAP DACs has an associated P CAP DAC and an N CAP DAC, a method includes generating voltage differences between P CAP DACs and N CAP DACs such that they produce M threshold voltages. The plurality of conversion engines operate in a first phase of the conversion by inputting the produced M threshold voltages to associated inputs of M comparators so that more than one bit can be determined from a sampled signal during each successive approximation trial. The plurality of conversion engines operate in a second phase of the conversion by inputting the produced M threshold voltages into the associated inputs of the M comparators such that the plurality of conversion engines operate independently so that fewer bits are determined from the sampled signal during each successive approximation trial then were determined during the first phase. A result obtained from at least one of the plurality of conversion engines is then outputted.