The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2010
Filed:
Jul. 25, 2007
Chae-iyoung Kim, Yongin-si, KR;
Chang-ki Hong, Seongnam-si, KR;
Bo-un Yoon, Seoul, KR;
Sung-ho Shin, Yongin-si, KR;
Byoung-ho Kwon, Suwon-si, KR;
Chae-Iyoung Kim, Yongin-si, KR;
Chang-ki Hong, Seongnam-si, KR;
Bo-un Yoon, Seoul, KR;
Sung-ho Shin, Yongin-si, KR;
Byoung-ho Kwon, Suwon-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.