The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2010
Filed:
Oct. 26, 2006
Sridhar Kailasam, Fremont, CA (US);
Robert Rozbicki, San Francisco, CA (US);
Chentao Yu, Sunnyvale, CA (US);
Douglas Hayden, San Jose, CA (US);
Sridhar Kailasam, Fremont, CA (US);
Robert Rozbicki, San Francisco, CA (US);
Chentao Yu, Sunnyvale, CA (US);
Douglas Hayden, San Jose, CA (US);
Novellus Systems, Inc., San Jose, CA (US);
Abstract
Methods of resputtering material from the wafer surface include at least one operation of resputtering material under a pressure of at least 10 mTorr. The methods can be used in conjunction with an iPVD apparatus, such as hollow cathode magnetron (HCM) or planar magnetron. The resputtered material may be a diffusion barrier material or a conductive layer material. The methods provide process conditions which minimize the damage to the dielectric layer during resputtering. The methods allow considerable etching of the diffusion barrier material at the via bottom, while not damaging exposed dielectric elsewhere on the wafer. Specifically, they provide a solution for the dielectric microtrenching problem occurring during conventional resputter process. Furthermore, the methods increase the etch rate to deposition rate ratio (E/D) and improve the etch back nonuniformity (EBNU) of resputter process. In general, the methods provide IC devices with higher reliability and decrease wafer manufacturing costs.