The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2010

Filed:

Dec. 05, 2007
Applicants:

Ishwardutt Parulkar, San Francisco, CA (US);

Gaurav H. Agarwal, Santa Clara, CA (US);

Krishna B. Rajan, Fremont, CA (US);

Paul J. Dickinson, San Jose, CA (US);

Inventors:

Ishwardutt Parulkar, San Francisco, CA (US);

Gaurav H. Agarwal, Santa Clara, CA (US);

Krishna B. Rajan, Fremont, CA (US);

Paul J. Dickinson, San Jose, CA (US);

Assignee:

Oracle America, Inc., Redwood City, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.


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