The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2010
Filed:
Nov. 29, 2007
Cong-feng Wei, Taipei Hsien, TW;
Po-chang Wang, Taipei Hsien, TW;
Fu-chuan Chen, Taipei Hsien, TW;
Wei-yuan Chen, Taipei Hsien, TW;
Cong-Feng Wei, Taipei Hsien, TW;
Po-Chang Wang, Taipei Hsien, TW;
Fu-Chuan Chen, Taipei Hsien, TW;
Wei-Yuan Chen, Taipei Hsien, TW;
Hon Hai Precision Industry Co., Ltd., Tu-Cheng, Taipei Hsien, TW;
Abstract
A system for detecting a work status of a computer system is provided. The system includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD), a South Bridge chipset and a device driver. The device driver is configured for driving the Super I/O chipset to generate and send a start signal to the CPLD, and is further configured for driving the Super I/O chipset to periodically generate and send a test signal to the CPLD. The CPLD is configured for receiving the start signal and triggering a clock to start timing from an initial time, monitoring whether a predetermined amount of test signals have been received in a predetermined time, and is further configured for sending a reboot signal to the South Bridge chipset when the predetermined amount of test signals have not been received in the predetermined time. The South Bridge chipset is configured for rebooting the computer system when receiving the reboot signal. A related method is also provided.