Pipelined processing using option bits encoded in an instruction

Abstract

A processor and a method for executing VLIW instructions using pipeline execution wherein each VLIW instruction includes a plurality of instructions and wherein the pipeline includes at least the following stages: first and second instruction fetch stages, a pre-decode stage, an instruction dispatch stage, first and second decoding stages, an execution stage and a write-back stage. During the first instruction fetch stage the number of outstanding instructions is determined where these outstanding instructions are from previous VLIW instructions that have not yet been issued for execution. During the second instruction fetch stage a comparison is performed on whether the number of outstanding instructions is less then the number of instructions in a VLIW instruction where if the number of outstanding instructions is less than the number of instructions in an instruction packet then the next VLIW instruction is fetched and the outstanding instructions are shifted and aligned with the fetched VLIW instruction. During the pre-decode stage determining which instructions in each VLIW instruction are to be issued and in the dispatch stage feeding the instructions not issued back to the first instruction fetch stage such that the processor is updated as to the number of outstanding instructions.