The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2010
Filed:
Jun. 30, 2005
William M. Loh, Fremont, CA (US);
Ken Doniger, Menlo Park, CA (US);
Payman Zarkesh-ha, Milpitas, CA (US);
Jau-wen Chen, Milpitas, CA (US);
Choshu Ito, Milpitas, CA (US);
William M. Loh, Fremont, CA (US);
Ken Doniger, Menlo Park, CA (US);
Payman Zarkesh-Ha, Milpitas, CA (US);
Jau-Wen Chen, Milpitas, CA (US);
Choshu Ito, Milpitas, CA (US);
LSI Corporation, Milpitas, CA (US);
Abstract
A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.