The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2010

Filed:

Mar. 30, 2006
Applicants:

Hiroyuki Horibata, Gifu, JP;

Michiru Senda, Yokohama, JP;

Inventors:

Hiroyuki Horibata, Gifu, JP;

Michiru Senda, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. In this display, at least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting a first shift signal or a second shift signal to a second voltage supply source not turning on transistors of a logic composition circuit portion in response to an output signal received from a shift register circuit portion precedent thereto by at least two stages with respect to a scanning direction.


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