The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2010

Filed:

Feb. 24, 2006
Applicants:

Mark Adam Bachman, Sinking Spring, PA (US);

Donald Stephen Bitting, Sinking Spring, PA (US);

Daniel Patrick Chesire, Winter Garden, FL (US);

Taeho Kook, Orlando, FL (US);

Sailesh Mansinh Merchant, Macungie, PA (US);

Inventors:

Mark Adam Bachman, Sinking Spring, PA (US);

Donald Stephen Bitting, Sinking Spring, PA (US);

Daniel Patrick Chesire, Winter Garden, FL (US);

Taeho Kook, Orlando, FL (US);

Sailesh Mansinh Merchant, Macungie, PA (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/488 (2006.01);
U.S. Cl.
CPC ...
Abstract

A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad () disposed thereon. A passivation layer () overlies the upper surface. A second conductive pad () is disposed in an opening () in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure () encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.


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