Recessed gate transistor structure and method of forming the same

Abstract

Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.