The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2010
Filed:
Apr. 20, 2005
Alexander Nickel, Santa Clara, CA (US);
Suzette K. Pangrle, Cupertino, CA (US);
Steven C. Avanzino, Cupertino, CA (US);
Jeffrey Shields, Sunnyvale, CA (US);
Fei Wang, San Jose, CA (US);
Minh Tran, Milpitas, CA (US);
Juri H. Krieger, Brookline, MA (US);
Igor Sokolik, East Boston, MA (US);
Alexander Nickel, Santa Clara, CA (US);
Suzette K. Pangrle, Cupertino, CA (US);
Steven C. Avanzino, Cupertino, CA (US);
Jeffrey Shields, Sunnyvale, CA (US);
Fei Wang, San Jose, CA (US);
Minh Tran, Milpitas, CA (US);
Juri H. Krieger, Brookline, MA (US);
Igor Sokolik, East Boston, MA (US);
Spansion LLC, Sunnyvale, CA (US);
GlobalFoundries Inc., Grand Cayman, KY (US);
Abstract
Disclosed are methods and systems for improving cell-to-cell repeatability of electrical performance in memory cells. The methods involve forming an electrically non-conducting material having ordered porosity over a passive layer. The ordered porosity can facilitate formation of conductive channels through which charge carriers can migrate across the otherwise non-conductive layer to facilitate changing a state of a memory cell. A barrier layer can optionally be formed over the non-conductive layer, and can have ordered porosity oriented in a manner substantially perpendicular to the conductive channels such that charge carries migrating across the non-conductive layer cannot permeate the barrier layer. The methods provide for the manufacture of microelectronic devices with cost-effective and electrically reliable memory cells.