The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7774723 B1

Date of Patent:

Aug. 10, 2010

Filed:

Mar. 09, 2007

Protecting trade secrets during the design and configuration of an integrated circuit semiconductor design

Applicant:

Soumya Banerjee, San Jose, CA (US);

Inventor:

Soumya Banerjee, San Jose, CA (US);

Assignee:

MIPS Technologies, Inc., Sunnyvale, CA (US);

Attorney:

Townsend and Townsend and Crew LLP

Primary Examiner:

Jack Chiang

Assistant Examiner:

Suchin Parihar

Int. Cl.

CPC ...

G06F 17/50 (2006.01);

U.S. Cl.

CPC ...

Abstract

A system and method for facilitating the design process of an integrated circuits (IC) is described. The system and method utilizes a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the IC. Synthesizable RTL is securely maintained on a server in a data center while providing designers graphical access to customizable IP block by way of a network portal.

Find Patent Forward Citations

Banerjee, Soumya. (2010). Protecting trade secrets during the design and configuration of an integrated circuit semiconductor design (U.S. Patent No. 7774723). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7774723

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