Nor flash memory device with a serial sensing operation and method of sensing data bits in a nor flash memory device

Abstract

In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.